On-Chip Generation and Detection of THz Waves with Orbital-Angular MomentumRuonan HanMITRuonan Han received his B.S. degree from Fudan University in 2007 and Ph.D. degree from Cornell University in 2014. He is now a tenured associate professor at MIT. His research group focuses on RF-to-photonics integrated systems for spectroscopy, metrology, imaging, quantum sensing/ processing, broadband/secure communication, etc. He is an associate editor of IEEE Trans. Very-Large-Scale Integration System and IEEE Trans. Quantum Engineering, and also serves on the Technical Program Committee of IEEE RFIC Symposium and the Steering Committee of IEEE International Microwave Symposium. He and his students have won three best student paper awards (2012, 2017 and 2021) in the RFIC symposium. He is the IEEE MTT-S Distinguished Microwave Lecturer in 2020-2022, and the winner of the Intel Outstanding Researcher Award in 2019 and the National Science Foundation CAREER Award in 2017.Information can be encoded into many different properties of an electromagnetic wave, including not only frequency, intensity, phase and polarization, but also certain helical phase distribution of its wavefront, namely the orbital angular momentum or OAM. Here we report the first chip-based demonstration (at any frequency) of a transceiver front-end that transmit and receives OAM waves. The CMOS chip consists of eight reconfigurable 0.31THz modulator/detector units, with integrated patch antennas placed in a uniform circular pattern. A full-silicon OAM link using a pair of such chips is demonstrated. The transmitted wave, controlled by an input data stream, can switch among the m=0 (plane wave), m=+1 (left handed), m=-1 (right handed) and superposition m=(+1)+(-1) states. Through such dynamic bit-to-OAM mode switching and the highly-angle sensitive OAM transmission, the link showcases the potential applications in the high-security, one-way transmission of encryption keys.
Cryogenic CMOS Controller for Large-Scale Quantum Computers: from Specifications to Implementation and Qubit TestingMasoud BabaieDelft University of TechnologyMasoud Babaie is currently a tenured Assistant Professor at the Delft University of Technology, Delft, The Netherlands. His research interests include RF/millimeter-wave integrated circuits for wireless communications and cryogenic electronics for quantum computation.
Dr. Babaie currently serves as a technical program committee (TPC) member of the ISSCC and ESSCIRC conferences. He was a co-recipient of the 2019 IEEE ISSCC Best Demo Award and the 2020 IEEE ISSCC Jan Van Vessem Award. In 2019, he received the Veni Award from the Netherlands organization for scientific research.A fault-tolerant quantum computer operates at deep cryogenic temperatures (typically 20-100mK) and requires massive yet very precise control electronics for the manipulation and read-out of individual quantum bits (qubits). The most complex state-of-the-art quantum computer (with 53 qubits) requires tens of bulky custom-made electronic modules operating at room temperature and connected to cryogenic qubits via hundreds of coaxial cables. However, this approach is not practical for implementing fault-tolerant quantum computers with millions of qubits due to the utter interconnect complexity, poor system scalability, and reliability. A better alternative would be to integrate the qubits and the control electronics on the same die or package and operate them at the same temperature. Toward this goal, electronics able to operate at cryogenic temperatures in close proximity to the qubits must be developed.
In this presentation, the essential functionalities required to control spin qubits and system-level specifications of the electronics are firstly discussed. Then, we review the characteristics and behavior of CMOS active and passive components at cryogenic temperatures. By exploiting the developed CMOS and qubit models, we develop the block diagram and circuit schematic of a digitally-intensive wideband transmitter capable of operating at 3K and controlling 32 frequency-multiplexed qubits. It also offers waveform shaping flexibility, minimum execution latency, and straightforward integration in the existing quantum computing stack. Finally, the cryogenic controller is used to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.
A CMOS Annealing Machine to Solve Combinatorial Optimization ProblemsMasanao YamaokaHitachi, Ltd.Masanao Yamaoka received the B.E., M.E., and Ph. D degrees in electronics and communication engineering from Kyoto University, Kyoto, Japan, in 1996, 1998, and 2007, respectively.
In 1998, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, where he was engaged in the research and development on low-power embedded SRAM and CMOS circuits. Since 2012, he has been engaged in the research of new-paradigm computing using CMOS circuits.To achieve the SDGs by IT technologies, various data processing technologies to solve various problems are required. One of the important processes is optimization to decide control parameters. For the optimization processing, new computing technologies are necessary to efficiently handle combinatorial optimization problems. The dramatic development of a general-purpose computers such as processors will be saturated in the near future due to the slow-down of the semiconductor scaling, and domain specific computing is expected to be the promising technologies. The CMOS annealing machine we have proposed is a new computing technology whose function is specialized only to combinatorial optimization processing. In this talk, the outline of the CMOS annealing machine is presented. The CMOS annealing is now commercializing phase, and its use cases in the real applications are also presented.
A Fully Implanted BMI (Brain-Machine Interface)Dongjin SeoNeuralink CorporationDJ Seo received his B.S in electrical engineering from California Institute of Technology (Caltech) with a focus on integrated circuit design for next-generation wireless communication systems and M.S. and Ph.D. from UC Berkeley for his work on ultrasonic wireless neural implant technology called neural dust. After his graduation, he helped start Neuralink, where he is currently VP of implant. His team works on all aspects of implant, from design and fabrication of electrode arrays that can be manipulated by surgical robot to on-chip neural signal processing engine, wireless data telemetry, powering, and hermetic packaging. Brain-machine interfaces (BMIs) hold promise for the restoration of sensory and motor function and the treatment of neurological disorders. Neuralink is building a fully implantable, minimally invasive BMI to enable a wider adoption of such clinical BMIs. This talk will describe the components of this BMI (including micron-scale electrodes, integrated electronics with wireless power and data telemetry, and a robotic neurosurgical device), how they address the key engineering challenges in building a scalable BMI, and applications of this technology.
Latest New & Hot Issue Forum Sub-committee Chair/Co-chair and Members
Minkyu Je, Chair KAIST, Korea
Youngjoo Lee, Co-Chair POSTECH, Korea
Stefan Rusu TSMC North America, USA
Jerald Yoo National University of Singapore
Surhud Khare Intel
Kaz Arimoto Okayama Prefectural University, Japan
Junghwan Choi Samsung Electronics, Korea
Pei-Yun Tsai National Central University, Taiwan, ROC