Trend, Hurdle, and Core Technologies For Next Generation High Performance Storage SystemChi-Weon YoonSamsung ElectronicsChi-Weon Yoon is a Vice President of Technology in Samsung Electronics, Hwa-sung, Korea. He received M.S and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1999 and 2004 respectively. After receiving the degree, he joined Samsung Electronics and have worked for more than 16 years at Flash Memory Design Team. He holds over 110 global patents about non-volatile memory related circuits and cell operation algorithms. His current research interests include design of high performance and low cost cell-operation algorithms, analog circuits and high speed I/O circuits.It is obvious that high performance data storage system will be a key enabler in upcoming 4th industrial revolution. NAND flash memory and storage system design technologies also have evolved in terms of more bit density and higher performance to meet demands. But the technology is now facing several technical hurdles as the device technology continues to scale down and requirements from market is becoming harsher.
In this talk, design challenges and solutions for implementing of high-performance data storage system will be covered. More Specifically, Issues and state-of-the-art technologies for next generation NAND flash memories will be discussed in detail, followed by an introduction of a frequency boosting chip solution for high speed and capacity storage system implementation.
Challenges and opportunities for in-memory/near-memory computing and AI acceleratorsRam KrishnamurthyIntel CorporationRam K. Krishnamurthy received the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA, in 1997. He has been at Intel Corporation since 1997. He is currently a Senior Principal Engineer at Intel Labs, Hillsboro, OR, USA, where he heads the High-Performance and Low-Voltage Circuits Research Group. In this role, he leads research in high-performance, energy-efficient, and low-voltage circuits for next generation microprocessors, accelerators, and Systems-On-Chip (SoCs). He holds 200 issued patents and has published 200 papers and four book chapters on high-performance and energy-efficient circuits. He has received two Intel Achievement Awards, the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award, and the IEEE European Solid State Circuits Conference Best Paper Award. He is a Fellow of the IEEE.This presentation will highlight some of the emerging challenges and opportunities for sub-5nm process machine learning and AI technologies in the rapidly evolving IoT industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and energy-efficient deep neural networks. New and emerging IoT markets for autonomous vehicles, drones, and wearables require even higher performance at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient AI processors and SoCs in the sub-5nm technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for in-memory and near-memory computing, reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic, memory and clocking circuits, AI inference accelerators including binary neural networks and associated on-chip interconnect fabric circuits are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.
A quantitative method to assess ROI of new silicon features in the context of SoC productHarry MuljonoIntelHarry Muljono is a Principal Engineer in the Xeon Product Group at Intel Corporation, where he leads a back-end team for future generation processors. Harry started his career in 1992 as an IO designer for Intel’s i486-DX2 processor, followed by Pentium® II, Itanium® and successive Xeon® processors. He holds 50 US patents with more pending in the area of analog circuits/DFx and has co-authored 20 conference and IEEE journal papers. Harry received a B.S. in Electrical Engineering degree from University of Portland, Portland, OR and an M.Eng. in Electrical Engineering degree from Cornell University, Ithaca, NY.A methodology is proposed to quantify a range of silicon metrics (power, area, performance, etc) in terms of SoC product cost. The result leads to a scoring index that can be used to assess ROI of specific silicon features in the context of SoC design process, assisting product decision making in a competitive market.
Computer Vision Hardware AcceleratorsKevin Ke XuSANECHIPS TECHNOLOGY CO., LTDDr. Ke Xu got the B.S. and M.S. degrees in Electrical Engineering Department from Fudan University, Shanghai, China, in 2000 and 2003, respectively, and the Ph.D. degree with Outstanding Award from the Department of Electronic Engineering, The Chinese University of Hong Kong in 2007. He was also the Post-doctoral Research Fellow in Department of Electrical and Computer Engineering in University of Toronto in 2009.
He served various senior roles as Staff/Algorithm Engineer, Chip Architect, Research Scientist, in different companies from startups to Fortune 500 such as IBM and Qualcomm, in China, Canada and USA. As key R &D; member for Snapdragon 810/820/835 development in Qualcomm headquarter in San Diego, he was in charge of computer vision and video processing system design. He joined ZTE Microelectronics in 2015 as AI Chief Scientist and Director of Engineering, where he is in charge of AI, autonomous driving, and multimedia chip designs. He led a R&D; group of more than 100 engineers with tens of technical experts. He developed several multimedia SoCs including smart phone, IPTV, IPC with advanced technology. He is also the Principal Researcher in State Key Laboratory of Mobile Network and Mobile Multimedia Technology. His expertise includes artificial intelligence, computer vision, virtual/augmented reality, computer architecture, multimedia technology, and VLSI design. He published more than 20 papers in international journals and conferences, and more than 20 patents holding.Computer Vision (CV) is one of the most important research area of artificial intelligence. With the rapid development of deep neural networks, the computation for vision tasks become extremely complex and time-consuming. As the Moore’s Law slows down or even comes to an end, how to accelerate vision computing using domain specific accelerators is essential to both algorithm and hardware designers. This talk aims to provide an overview of CV hardware architectures, and the techniques being explored to efficiently accelerate the computation. It addresses and compares various state-of-the-art domain specific architectures and implementations.
Industry Forum Sub-committee Chairs and Members
Jerald Yoo, Chairs National University of Singapore
Surhud Khare, Chairs Intel
Subcommittee Members
Stefan Rusu TSMC North America, USA
Kaz Arimoto Okayama Prefectural University, Japan
Junghwan Choi Samsung Electronics, Korea
Pei-Yun Tsai National Central University, Taiwan, ROC
Challenges and opportunities for in-memory/near-memory computing and AI accelerators
Ram Krishnamurthy
Intel Corporation
A quantitative method to assess ROI of new silicon features in the context of SoC product
Harry Muljono
Intel
Computer Vision Hardware Accelerators
Kevin Ke Xu
SANECHIPS TECHNOLOGY CO., LTD