ESSCIRC Joint Session

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  Tuesday, November 9

  A −109.1 dB/−98 dB THD/THD+N Chopper Class-D Amplifier with >83.7 dB PSRR Over the Entire Audio Band Huajun Zhang Delft Univ of Technology Biography Abstract Huajun Zhang received the B.E. degree in electrical and computer engineering from Shanghai Jiao Tong University, Shanghai, China, in 2015, and the B.S.E. and M.S. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2015 and 2017, respectively. From May 2017 to February 2019, he was a Mixed Signal Design Engineer with Analog Devices, Inc., Norwood, MA, USA. He is currently pursuing the Ph.D. degree with the Delft University of Technology, Delft, The Netherlands, working on Class-D audio amplifiers. This paper reports a chopper Class-D audio amplifier that obtains high PSRR over the entire audio band. A chopping scheme is proposed to minimize intermodulation distortion between pulse-width modulation (PWM) and chopping in the audio band. A high-voltage chopper is developed to handle a 14.4 V PWM signal. Timing matching techniques are proposed to minimize chopping nonidealities which ensure good PSRR and THD. Fabricated in a 180nm BCD process, the prototype obtains a PSRR >109 dB at 217 Hz and >83.7 dB over the entire audio band. It also achieves −109.1 dB/−98 dB THD/THD+N and can deliver a maximum of 13 W to an 8-Ω load.
• A 67mW D-Band FMCW I/Q Radar Receiver with an N-Path Spillover Notch Filter in 28nm CMOS Anirudh Kankuppe Imec / Free University of Brussels Biography Abstract Anirudh Kankuppe received the M.Sc. degree in Microelectronics and Microsystems from the Hamburg University of Technology, Hamburg, Germany in 2017. He was a Design Engineer with Cadence Design systems, India from 2012 to 2014. During his M.Sc., he was a recipient of Gifted Student Scholarship from TU Hamburg and National Merit Scholarship from Government of India in 2005. He is pursuing a Ph.D. in mm-wave and RF integrated circuits with Vrije Universiteit Brussel, Brussels, Belgium in collaboration with imec, Leuven, Belgium and currently working as a Researcher in the Advanced RF group at imec, Leuven, Belgium. His research is focused on mm-wave radar circuits, receivers and wireline ADCs. A 139.5-157.7 GHz D-band I/Q radar receiver with an on-chip antenna and a spillover resilient N-path baseband filter is presented. Spillover and its manifestation based on the chirp rate is discussed and a filter for spillover mitigation is implemented. The radar is characterized with 55 dB conversion gain, 8dB NF (5.6 dB EINF) and 26dB narrow-band spillover attenuation. The receiver is also capable of selectively mitigating very close-by large reflectors and the system power consumption is 67mW.
• A Resolution-Adaptive 8mm2 9.98Gb/S 39.7pJ/B 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS Oscar Castaneda ETH Zurich Biography Abstract Oscar Castañeda received his M.Sc. degree in Electrical and Computer Engineering from Cornell University in 2020. He is currently a Ph.D. Candidate in the Integrated Information Processing (IIP) group at the Department of Information Technology and Electrical Engineering, ETH Zürich. In 2019, he received a Qualcomm Innovation Fellowship, as well as a Top 10 Best Student Presentation Award at SRC TECHCON. His research interests include digital signal processing, emerging computer architectures, and digital VLSI circuit and system design. All-digital millimeter-wave massive multi-user MIMO receivers enable extreme data-rates but require high power consumption. To reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband processing to the instantaneous communication scenario. The scalable 32-antenna, 65nm CMOS receiver occupies a total area of 8mm² and integrates ADCs with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98Gb/s while being at least 2x more energy-efficient than state-of-the-art designs.
• A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band Rejection Amir Bozorg UC Dublin Biography Abstract Amir Bozorg received the M.Sc. degree (with Hons.) in Microelectronics from Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran in 2012 and his Ph.D. in Electrical engineering from University College Dublin (UCD), Ireland in 2021. From 2016 to 2018, he was consulting for TSMC, Hsinchu, Taiwan, on a 16-nm ADPLL/RX for automotive radar applications. From 2017 to 2020 he was working as an R&D; Scientist at S3 Semiconductor (now Dialog Semiconductor) Dublin, Ireland, where he was developing a K-band phased-array receiver. He has also raised venture capital from Atlantic Bridge Ventures, Dublin, Ireland, for commercializing an ADPLL-based phased-array transmitter for automotive radars. Since 2020 he has been working with Equal1 Labs Ltd. in Dublin, Ireland as a Research Scientist. He has authored or coauthored several IEEE journal papers, an upcoming book on discrete-time receivers, and holds four issued U.S. patents in the field of RF-CMOS design. His research interests include millimeter-wave/RF transceivers, discrete-time receivers, ADPLLs, and oscillators. This paper introduces a new architecture of a discrete-time charge-rotating low-pass filter (LPF) which achieves a high-order of filtering and improves its stop-band rejection while maintaining a reasonable duty cycle of the main clock at 20%. Its key innovation is a linear interpolation within the charge-accumulation operation. Fabricated in 28-nm CMOS, the proposed IIR LPF demonstrates a 1--9.9 MHz bandwidth programmability and achieves a record-high 120 dB stop-band rejection at 100 MHz while consuming merely 0.92 mW. The in/out-of-band IIP3 is +18.6/+26.6 dBm.
• 200-GS/S ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator Gregory Cooke Univ of Toronto Biography Abstract Gregory Cooke is a MASc. candidate at the University of Toronto under Prof. Sorin P. Voinigescu. He is working on high-bandwidth, high-sampling rate ADC frontend circuits for fiber-optic network applications in SiGe BiCMOS. A 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 25.3 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25%duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.

IT Vision in Asia Sub-committee Chair/Co-chair

• Robert Chen-Hao Chang, Chair National Chung Hsing University, Taiwan
• Giovanni Mangraviti, Co-Chair IMEC, Belgium