RiSE(Rising Star Express) Forum

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  Wednesday, November 10

  Analog to the Rescue? Analog Deep Learning Accelerator Aspects and Challenges Kentaro Yoshioka Assistant Professor, Keio University, Japan Biography Abstract Kentaro Yoshioka received his BS, MS, Ph.D degrees from Keio University, Japan. Currently, he is an Assistant Professor at Keio
  University. He worked with Toshiba during 2014-2021, developing circuitry for WiFi and LiDAR SoCs. During 2017-2018, he had been a visiting scholar at Stanford University, exploring efficient machine learning hardware and algorithms. He was the recipient of ASP-DAC 2013 Special Feature Award, the A-SSCC 2012 Best Design Award, and 1st place winner of Kaggle 2020 PANDA Challenge. Low-powered Deep Learning Accelerators (DLAs) are required for battery driven IoT devices. Significant research efforts have been poured into digital-based DLAs, improving the efficiency in order of magnitude-but can we expect even more dramatic improvements? DNNs can tolerate low-precision operations; another 10x efficiency improvements are possible by leveraging analog-based approximate computing.
  In this talk, we will discuss the advantages and challenges of bit-serial analog DLAs, also known as computing in memory, and phase-based bit-parallel analog DLAs.
• Circuit and System Innovations Towards Robust and Secure Millimeter-Scale Bioelectronic Implants Kaiyuan Yang Assistant Professor, Rice University Biography Abstract Kaiyuan Yang received his B.S. in Electronic Engineering from Tsinghua University, China, in 2012, and his Ph.D. degree in Electrical Engineering from the University of Michigan, Ann Arbor, MI, in 2017. His Ph.D. research was recognized with the 2016 IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award.
  He has been an Assistant Professor of ECE at Rice University, USA, since 2017. His research interests include digital and mixed-signal circuits for secure, intelligent and low-power microsystems, hardware security, and circuit/system design with emerging devices. Dr. Yang received a number of best paper awards from top-tier conferences in multiple fields, including the Best Paper Award at the 2021 IEEE Custom Integrated Circuit Conference (CICC), Distinguished Paper Award at the 2016 IEEE International Symposium on Security and Privacy (Oakland), Best Student Paper Award (1st place) at the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), and the Best Student Paper Award finalist at the 2019 IEEE Custom Integrated Circuit Conference (CICC). Millimeter-scale bioelectronic implants promise transformative applications in medicine, health, and scientific research. This talk will overview our recent progress on unconventional hardware designs to enable several critical properties and functions for bio implants, satisfying the unprecedented power, volume, and wireless requirements. More specifically, we blur digital and analog domains in circuit and system designs, to push the frontier in safe and robust power delivery, low-power yet high-performance analog blocks, and hardware security primitives to protect these extremely miniaturized devices.
• Power Management Integrated Circuits using Switched Inductor/Capacitor Converters Se-Un Shin Assistant Professor, UNIST, Korea Biography Abstract Se-Un Shin received the B.S. degree in electronics engineering from Kyungpook National University, Daegu, South Korea, in 2013, and the integrated master’s and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2018. From 2018 to 2019, he was a Postdoctoral Associate with the University of Michigan, Ann Arbor, MI, USA. From 2019 to 2020, he was a Faculty with the Department of Display Engineering, Dankook University, Cheonan, South Korea. Since 2021, he has been with Electrical Engineering in UNIST, where he is currently an Assistant Professor. His current research interests include analog integrated circuit design and power management IC design, energy harvesting, battery charger, wireless power transfer systems, switched capacitor/inductive converters, and hybrid converter topology. Prof. Shin was a recipient of the Bronze Prize and Silver Prize in the 22nd and 24th Human-Tech Thesis Prize Contest from Samsung Electronics, in 2016 and 2018, respectively, and the IEEE Solid-State Circuits Society Predoctoral Achievement Award in 2018. In this presentation, dual-path converters are presented for achieving high power efficiency in the mobile power management ICs (PMICs). Adopting a hybrid structure using one inductor and one flying capacitor, the proposed converters supply a load current via two parallel paths, relieved intrinsic problems of the conventional converter topology. The proposed converters can achieve a high power efficiency and thus also reduce the heating problem, which is another critical issue in the mobile set. Moreover, it can shrink the volume of the PMIC set with a low manufacturing cost.
• Millimeter-wave and Terahertz Multifunctional CMOS Transceiver for Future Sensing/Communication Fusion-mode Wireless System Wei Deng Associate Professor, Tsinghua University, Beijing, China Biography Abstract Wei Deng received the B.S. and M.S. degrees from University of Electronic Science and Technology of China, China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. From 2013 to 2014, he was a Post-Doctoral Researcher with the Tokyo Institute of Technology. From 2015 to 2019, he was with Apple Inc., Cupertino, USA, working on mm-wave and mixed-signal IC design for wireless transceivers and A-series processors. Since 2019, he has been a faculty member with Tsinghua University, China. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and system. He currently serves as a TPC Member for ISSCC, VLSI, and ESSCIRC. Recent years, millimeter-wave and Terahertz radar systems for sensing and radio systems for communication have attracted substantial attention both from the academia and industry. In addition, there is an increasing demanding for fusing both the hardware platform and frequency band of the radar and radio system, which has advantages of energy efficiency, performance optimization, spectrum sharing/efficiency, compact size, interference management, and the overall cost, as compared to assembling of two distinct systems. In this talk, a D-band radar/communication fusion-mode transceiver in 28nm CMOS technology, which is suitable for performing high-resolution range measurement and high data rate wireless transmission on one single chip, is introduced for future radar-communication joint wireless system.
• FPGA-based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator Ka-Fai Un Assistant Professor, University of Macau Biography Abstract Ka-Fai Un received the B.Sc. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2007, and the M.Sc. degree in electrical and electronics engineering and the Ph.D. degree from the University of Macau (UM), Macau, in 2009 and 2014, respectively. Dr. Un was a Post-Doctoral Researcher and a Lecturer (Macao Fellow) in 2014 and 2015, respectively. He is an assistant professor since 2018 all with the State Key Laboratory of Analog and Mixed-Signal VLSI, UM. He was on leave from UM and was a visiting Post-Doctoral Researcher with the School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland, from 2017 to 2018. His research interests are analog and RF circuit design, analog artificial intelligence circuit design and digital neural network accelerator. The computational efficiency is the prime concern of a computation-intensive deep convolutional neural network (CNN) accelerator. The memory access power is as significant as the computational power in a neural network accelerator. Reducing repeated memory accesses to input activations/weights is crucial for designing energy- efficient accelerators. In this presentation, we summarize the considerations for designing energy-efficient FPGA-based accelerators. Recent accelerator research conducted by our research group is introduced to demonstrate the importance of the dataflow management for reducing memory accesses. Further methods which can increase the computational efficiency are also introduced.

RiSE(Rising Star Express) Forum Sub-committee Chair/Co-chair and Members

• Mototsugu Hamada, Chair Univ. of Tokyo, Japan
• Jaehyouk Choi, Co-Chair KAIST, Korea

Subcommittee Members

• Vanessa Chen Carnegie Mellon University
• Yong Chen University of Macau
• Yan Zhu University of Macau